Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory.
Flash memory devices have developed into a popular source of non-volatile memory for a wide range of electronic applications. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Changes in threshold voltage of the cells, through programming of charge storage nodes, such as trapping layers or other physical phenomena (which is sometimes referred to as writing), determine the data value of each cell. Common uses for flash memory include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, cellular telephones, and removable memory modules.
A NAND flash memory device is a common type of flash memory device, so called for the logical form in which the basic memory cell configuration is arranged. Typically, the array of memory cells for NAND flash memory devices is arranged such that the control gate of each memory cell of a row of the array is connected together to form an access line, such as a word line. Columns of the array include strings (often termed NAND strings) of memory cells connected together in series, source to drain, between a pair of select lines, a source select line and a drain select line. The source select line includes a source select gate at each intersection between a NAND string and the source select line, and the drain select line includes a drain select gate at each intersection between a NAND string and the drain select line. The select gates are typically field-effect transistors. Each source select gate is connected to a source line, while each drain select gate is connected to a data line, such as column bit line.
The memory array is accessed by a row decoder activating a row of memory cells by selecting the word line connected to a control gate of a memory cell. In addition, the word lines connected to the control gates of unselected memory cells of each string are driven to operate the unselected memory cells of each string as pass transistors, so that they pass current in a manner that is unrestricted by their stored data values. Current then flows from the column bit line to the source line through each NAND string via the corresponding select gates, restricted only by the selected memory cells of each string. This places the current-encoded data values of the row of selected memory cells on the column bit lines.
A memory device is usually placed in communication with a controller, such as a processor, a host controller, or other external host device via an input/output interface, e.g., to form part of an electronic system. The memory device receives control signals, command signals (which are sometimes referred to as commands), address signals (which are sometimes referred to as addresses), and data signals (which are sometimes referred to as data) from the controller and outputs data to the controller.
Defects can occur during the manufacture of a memory array having rows and columns of memory cells, resulting in defective rows or columns. This problem is commonly solved by incorporating redundant elements in the memory that selectively replace defective elements. Redundant rows are a common form of redundant elements used in flash memory to replace defective primary rows. For example, for NAND flash memory arrays, blocks of redundant rows (commonly referred to as a redundant blocks) replace defective blocks of primary rows (commonly referred to as a primary blocks).
Redundant blocks are typically located in a different portion of a memory array than the primary blocks. Generally, redundancy circuitry is used to selectively route access requests directed to the defective primary blocks to the redundant blocks located in a different portion of the array. Some memory devices, including some flash memory devices, utilize non-volatile registers to store addresses of primary blocks that are designated to be replaced. Address requests from the host controller are compared to the addresses of the defective primary blocks stored in the registers at the memory device, e.g., by the redundancy circuitry. If an address request matches an address of a defective primary block stored in the register, the redundancy circuitry directs or maps the access request to the redundant block instead of the defective primary block.
The process of replacing a defective primary block with a redundant block is typically transparent to the host controller in that the host controller does not know the address it sends to the memory device is an address of a defective block. That is, the host controller believes it is accessing a memory block at a location in the memory array (the location of the defective block) corresponding to the address that the host controller sends to the memory device. Instead, the host controller is accessing a redundant block located at a different location within the array.
There is typically a voltage delay along the length of a word line when a voltage is applied to the word line due to resistive and capacitive effects (commonly referred to as an RC delay). The RC delay increases with increasing distance from the end of the word line to which the voltage is applied, e.g., from the end closest to the row decoder. Moreover, there is typically a voltage delay along the bit line, with the delay increasing with increasing distance along the bit line from a sense amplifier.
In some instances, the host controller may be programmed to compensate for the voltage delay at a memory cell due to the distance of the memory cell from the row decoder and/or the sense amplifier. However, problems can occur if the block containing memory cells that are being compensated for is a defective block whose address is mapped to a redundant block located at a different location in the array. This is because the host controller is programmed to compensate for the delay based on the location of the defective memory block within the array and not on the location of the redundant block. That is, the compensation will be applied to the memory cells in the redundant block as though they were located at the location of the defective block.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for alternative redundancy schemes.